To achieve better noise performance, the filter of a phase locked loop (PLL) is generally composed of passive components. In low-bandwidth applications, the passive filter has a larger capacitance, so that it takes a long time for the PLL to implement the locking. To comply with the system locking time requirement and retain the low-bandwidth of the PLL, the general practice is adding a fast locking circuit to stabilize the PLL in the shortest time.
FIG. 1 illustrates a general PLL with the fast locking circuit in the prior art. To add a fast locking circuit, a P-type field effect transistor 102 (marked as MP1) is connected to the filter 101 of the PLL. The grid electrode of the MP1 must be connected to a control signal (marked as input in FIG. 1). When the PLL begins to work, the input is low level, and the MP1 is open. As shown in FIG. 1, the size of the MP1 is generally large. The purpose is to ensure that the MP1 can supply sufficient current to the capacitor of the filter 101 when the MP1 is open. The VCTRL voltage in the loop is unknown at the beginning because the residual charge on the capacitor of the filter 101 is unknown (perhaps the residual charge is 0 V or a fixed value). After the MP1 is open, the VCTRL voltage increases when the capacitor of the filter 101 is charged continuously. The MP1 is disconnected at a certain point of time when the input signal changes from low level to high level. In this case, the charging process is completed, and the VCTRL voltage on the filter 101 is a fixed value. Then, the PLL starts a formal locking process by using its negative feedback principle.
After analyzing the prior art, the inventor of the present invention discovers the following weaknesses of the fast locking circuit of the PLL in the prior art:
Because the VCTRL voltage on the filter cannot be determined in advance for the completion of charging, the fast locking circuit in the prior art cannot provide the PLL with a better VCTRL voltage to minimize the locking time of the PLL.